module regfile(
    input         clk,
    // READ PORT 1
    input  [ 4:0] raddr1,
    output [63:0] rdata1,
    // READ PORT 2
    input  [ 4:0] raddr2,
    output [63:0] rdata2,
    //x1_port
    output [63:0] x1_value,
    // WRITE PORT
    input          we,       //write enable, HIGH valid
    input  [ 4:0] waddr,
    input  [63:0] wdata,
    output wire [`REG_BUS ] regs_o [31:0]
);
reg [63:0] rf[31:0];

//WRITE
// always @(posedge clk) begin
//     if (we) rf[waddr]<= wdata;
// end
always @(posedge clk) begin
        if (we & waddr != 0) rf[waddr]<= wdata;
end
//READ OUT 1
assign rdata1 = (raddr1==5'b0) ? 63'b0 : rf[raddr1];

//READ OUT 2
assign rdata2 = (raddr2==5'b0) ? 63'b0 : rf[raddr2];
//X1_port
assign x1_value = rf[5'h01];

genvar i;
	generate
		for (i = 0; i < 32; i = i + 1) begin
			assign regs_o[i] = (we & waddr == i & i != 0) ? wdata : rf[i];
		end
	endgenerate


endmodule

